1. Field of the Invention
The present invention generally relates to memory devices, and more particularly, the present invention relates charge trap flash memory device, a method of fabricating a charge trap flash memory device, and a write/read operation control method of a charge trap flash memory device.
A claim of priority is made to Korean Patent Application Nos. 10-2005-0096552 and 10-2005-0125643 filed Oct. 13, 2005, and Dec. 19, 2005, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.
2. Description of the Related Art
Flash memory combines advantages offered by an EPROM (Erasable Programmable ROM) and an EEPROM (Electrically Erasable Programmable ROM), including a significantly reduced cell area and electrical erasability. Unlike an EEPROM, however, flash memory cells can be erased and reprogrammed in blocks in a single operation, thereby offering faster erase and access operations.
A flash memory device is fabricated by sequentially laminating on a silicon substrate a thin tunnel oxide layer, a floating gate made of polysilicon, an integrated dielectric layer, and a control gate electrode to which a predetermined voltage is applied.
The floating gate of a commercially available flash memory device is generally made of polysilicon. However, a conventional polysilicon floating gate structure presents several limitations in achieving ultra-thin, large-scale devices, due to interference between memory cells, inefficiency of an increased number of operation steps, and so on.
As one of alternative attempts to achieve ultra-thin, large-scale devices, a method of forming Si nano-particles in an Si oxide film has been proposed. However, since the proposed method is based on ion implementation, the process is quite complex and only a small number of devices can be fabricated in an extremely high degree of clean environment, it is quite difficult to realize mass production and commercialization of the devices. Thus, the Si nano-particles for use in the conventional flash memory may decrease the fabrication efficiency and increase the fabrication cost.
Further, in order to enable a flash memory device using Si nano-particles to operate in multiple levels, which is necessary to store a large amount of information without increasing a device area, complicated peripheral circuits and an operation mechanism for accurately controlling write operation are required.